1. Field of the Invention
The present invention generally relates to the design of semiconductor integrated circuits (ICs) or of electronic packages and, more particularly, to an efficient procedure for modifying the design to allow the creation of fill shapes which are added to the design to correct for process deviations.
2. Description of the Prior Art
Semiconductor integrated circuits (ICs) and printed circuit packages typically are composed of structures consisting of several layers of conducting, insulating and other materials that are structured in the horizontal dimension by fabrication processes that transfer patterns defined in physical designs or layouts. The physical designs are represented by computer data representing two-dimensional shapes. The computer data are organized in a hierarchical data structure that exploits the repetitive structure usually found in circuits and packages.
In some cases, the action of the fabrication processes is affected by the design patterns being transferred to the physical materials. For example, the local pattern density of the design, i.e., the fraction of area over which material is deposited (or removed) can affect the shapes and dimensions of features, with the "locality extent" dependent on the specific fabrication process. As a specific example, this can occur in reactive ion etching (RIE), in which a deficiency in local pattern density (meaning that more material is to be etched away) causes the pattern features to be too large (i.e., "underetched") due to depletion of the etchants. This effect appears to act at a length scale of hundreds of micrometers to millimeters. Other processes that may be affected by local pattern density include lithographic patterning of resist materials and chemical-mechanical (so called "chemech" ) polishing.
There are a variety of approaches to solving this problem, some of which pertain to the fabrication process itself, while others work by modifying the physical design to mitigate the pattern-dependent effects. The approach of the latter type solution is to reduce deviations from design to fabricated part by adding fill shapes that have no electrical function but which reduce variations in local pattern density. There are several drawbacks to this approach including the possibility that fill shapes may affect electrical behavior/performance, fill shapes are difficult to add to the design manually and may be computationally costly to generate automatically, and fill shapes may significantly increase data size of the physical design, making subsequent data-handling steps (e.g., mask fracturing) more difficult.
U.S. Pat. No. 5,278,105 to Eden et al. describes the use of fill shapes for correcting process problems due to local pattern density deficiencies; however, there is no description of the method of generating those fill shapes. Without an efficient method for generating the fill shapes, the Eden et al. method is potentially very expensive to implement.